Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance

Author

Mehrotra, V. ; Nassif, S. ; Boning, D. ; Chung, J.

Author_Institution

MIT, Cambridge, MA, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

767

Lastpage

770

Abstract

This paper contributes the first study of manufacturing variation on interconnect timing performance in a high speed microprocessor. Also new in this paper is a methodology using timing analysis in conjunction with post-extraction net adjustment to account for interconnect structure variation (e.g., that arising due to pattern dependencies); this methodology is efficient enough to enable thousands of nets to be analyzed for variation and is compatible with current CAD tools.

Keywords

circuit simulation; high-speed integrated circuits; integrated circuit interconnections; integrated circuit manufacture; integrated circuit modelling; microprocessor chips; timing; high-speed microprocessor interconnect; interconnect structure variation; interconnect timing performance; manufacturing variation effects; microprocessor interconnect performance; post-extraction net adjustment; timing analysis; Capacitance; Circuit simulation; Data mining; Information geometry; Integrated circuit interconnections; Microprocessors; Pattern analysis; Solid modeling; Timing; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746469

Filename

746469