Author :
Chatterjee, A. ; Chapman, R.A. ; Joyner, K. ; Otobe, M. ; Hattangady, S. ; Bevan, M. ; Brown, G.A. ; Yang, H. ; He, Q. ; Rogers, D. ; Fang, S.J. ; Kraft, R. ; Rotondaro, A.L.P. ; Terry, M. ; Brennan, K. ; Aur, S.-W. ; Hu, J.C. ; Tsai, H.-L. ; Jones, P. ;
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Abstract :
This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO/sub 2/ but having relatively low gate leakage are reported. Transistors with gate lengths near or below 0.1 /spl mu/m have good characteristics. Working CMOS circuits using Ta/sub 2/O/sub 5/ gate insulator are demonstrated for the first time.
Keywords :
CMOS integrated circuits; MOSFET; capacitance; dielectric thin films; leakage currents; permittivity; 0.1 micron; CMOS metal replacement gate transistors; MOS devices; Ta/sub 2/O/sub 5/ gate insulator; TiN-W-Ta/sub 2/O/sub 5/-SiNO-Si; TiN/W metal replacement gate transistor design; full CMOS process; high dielectric constant gate insulator; high gate capacitances; low gate leakage; thin remote plasma nitrided gate oxide; CMOS process; Capacitance; Dielectrics and electrical insulation; Gate leakage; High-K gate dielectrics; MOS devices; Metal-insulator structures; Plasma devices; Plasma properties; Tin;
