PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

Author

Maiti, B. ; Tobin, P.J. ; Hobbs, C. ; Hegde, R.I. ; Huang, F. ; O´Meara, D.L. ; Jovanovic, D. ; Mendicino, M. ; Chen, J. ; Connelly, D. ; Adetutu, O. ; Mogab, J. ; Candelaria, J. ; La, L.B.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

781

Lastpage

784

Abstract

We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) metal gate integration on sub-quarter micron CMOSFETs using bulk Si and FDSOI substrates. In addition to eliminating poly depletion effects and lowering gate line resistance, the use of the TiN gate enables lower Vt when used with FDSOI substrates instead of bulk Si. Excellent on-off and short channel characteristics can be obtained with the TiN gate. Issues associated with Leff and reliability are also discussed.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit metallisation; integrated circuit reliability; silicon; silicon-on-insulator; substrates; titanium compounds; vapour deposited coatings; 0.25 micron; CMOSFETs; FDSOI substrates; PVD TiN metal gate MOSFETs; Si; TiN; bulk Si substrates; deep subquarter micron CMOS technology; effective channel length; fully depleted SOI substrates; gate line resistance reduction; physical vapor deposited TiN; poly depletion effects elimination; polysilicon capped MOSFET; reliability; short channel characteristics; Atherosclerosis; CMOS technology; Doping; Implants; Insulation; MOS devices; MOSFETs; Metal-insulator structures; Silicon; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746472

Filename

746472