High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime

Author

Yagishita, A. ; Saito, T. ; Nakajima, K. ; Inumiya, S. ; Akasaka, Y. ; Ozawa, Y. ; Minamihaba, G. ; Yano, H. ; Hieda, K. ; Suguro, K. ; Arikado, T. ; Okumura, K.

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

785

Lastpage

788

Abstract

We propose a plasma and thermal damage-free gate process named the "Damascene gate process" where CMP (Chemical Mechanical Polishing) is used in forming the gate structure. By using this process, fully planarized high performance metal (W/TiN or Al/TiN) gate transistors with pure SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were fabricated with very uniform and highly reliable electrical characteristics. Therefore, this technology is useful in fabricating 0.1 /spl mu/m MOSFETs and beyond.

Keywords

CMOS integrated circuits; MOSFET; ULSI; chemical mechanical polishing; integrated circuit metallisation; semiconductor device metallisation; 0.1 micron; Al-TiN; Al/TiN gate; CMOSFET; CMP fabrication; Damascene gate process; SiO/sub 2/; SiO/sub 2/ gate insulator; Ta/sub 2/O/sub 5/; Ta/sub 2/O/sub 5/ gate insulator; W-TiN; W/TiN gate; chemical mechanical polishing; high performance metal gate MOSFETs; plasma damage-free gate process; reliable electrical characteristics; thermal damage-free gate process; Annealing; Capacitance; Conductivity; Electrodes; MOSFETs; Plasma properties; Plasma temperature; Sputtering; Tin; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746473

Filename

746473