A high-throughput reconfigurable Viterbi decoder

Author

Li, Rongchun ; Dou, Yong ; Zhou, Jie ; Lei, Guoqing

Author_Institution

Comput. Sch., Nat. Univ. of Defense Technol., Changsha, China

fYear

2011

fDate

9-11 Nov. 2011

Firstpage

1

Lastpage

6

Abstract

A reconfigurable Viterbi decoder with high throughput and low complexity is presented in this paper. The proposed Viterbi decoder supports constraint lengths ranging from 3-9, code rates in the range of 1/2-1/3, and arbitrary truncation lengths. The decoder achieves a low bit error ratio in multiple standards, such as GPRS, WiMax, LTE, CDMA, and 3G. The proposed decoder is implemented on Xilinx XC5VLX330 device and the frequency achieved is 202 MHz with the throughput of 202 Mbps, which is apparently superior to the other current reconfigurable Viterbi decoders on the FPGA platform.

Keywords

Viterbi decoding; field programmable gate arrays; 3G; CDMA; FPGA platform; GPRS; LTE; WiMax; Xilinx XC5VLX330 device; arbitrary truncation lengths; bit error ratio; bit rate 202 Mbit/s; frequency 202 MHz; high-throughput reconfigurable Viterbi decoder; Bit error rate; Decoding; Fabrics; Field programmable gate arrays; Measurement; Throughput; Viterbi algorithm; FPGA; Viterbi Decoder; high-throughput; reconfigurable;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications and Signal Processing (WCSP), 2011 International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4577-1009-4

Electronic_ISBN

978-1-4577-1008-7

Type

conf

DOI

10.1109/WCSP.2011.6096781

Filename

6096781