(Ba,Sr)TiO/sub 3/ capacitor technology for Gbit-scale DRAMs

Author

Ono, K. ; Horikawa, T. ; Shibano, T. ; Mikami, N. ; Kuroiwa, T. ; Kawahara, T. ; Matsuno, S. ; Uchikawa, F. ; Satoh, S. ; Abe, H.

Author_Institution

Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

803

Lastpage

806

Abstract

Great efforts have been made for the integration of high dielectric constant (Ba,Sr)TiO/sub 3/ (BST) capacitors into DRAMs. This paper presents the current state of the art in BST capacitor technology for Gbit-scale DRAMs, with emphasis on key technical issues for process integration, including electrode materials, barrier layers, and also BST films themselves. The problems which may remain to be solved are also discussed to realize the goal: a barrier layer on top electrode for back-end processes, reliability of integrated BST capacitors, and further improvement of coverage properties of BST films and cell-plate metals.

Keywords

DRAM chips; barium compounds; capacitors; strontium compounds; (Ba,Sr)TiO/sub 3/ capacitor; BST film; BaSrTiO/sub 3/; DRAM; back-end process; barrier layer; cell-plate metal; dielectric constant; electrode material; process integration; reliability; Binary search trees; Capacitance; Capacitors; Dielectric materials; Dry etching; Electrodes; High-K gate dielectrics; Material storage; Random access memory; Sputter etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746477

Filename

746477