Integration processes of (Ba,Sr)TiO/sub 3/ capacitor for 1 Gb and beyond [DRAMs]

Author

Byoung Taek Lee ; Cha Young Yoo ; Han Jin Lim ; Chang Seok Kang ; Hong Bae Park ; Wan Don Kim ; Suk Ho Ju ; Horii, H. ; Ki Hoon Lee ; Hyun Woo Kim ; Sang In Lee ; Moon Young Lee

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

815

Lastpage

818

Abstract

A new two-step post-annealing process to prevent degradation of integrated BST capacitors was developed. By this process, the increment of capacitance and the reduction of leakage current were obtained without barrier oxidation. A concave-type capacitor structure with buried barrier using Pt electrodes and MOCVD BST films was demonstrated in order to solve the integration problems such as Pt etching and the contact between the BST and the barrier. The electrical properties of MOCVD BST capacitor in 3-dimensional structure were investigated.

Keywords

DRAM chips; MOCVD; barium compounds; capacitors; dielectric thin films; leakage currents; strontium compounds; (BaSr)TiO/sub 3/; 1 Gbit; DRAMs; MOCVD films; buried barrier; concave-type capacitor structure; etching; integrated capacitor degradation; leakage current; three-dimensional structure; two-step post-annealing process; Binary search trees; Capacitance; Capacitors; Contacts; Degradation; Electrodes; Etching; Leakage current; MOCVD; Oxidation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746480

Filename

746480