• DocumentCode
    2575364
  • Title

    A Novel Submodeling Scheme on Thermal Cycle Test for CMOS Image Sensor

  • Author

    Hsu, Hsiang-Chen ; Lee, Hui-Yu ; Hsu, Yu-Chia ; Hu, Chin-Yuan ; Lin, Ming-Jer ; Chin, Pei-Chieh ; Fu, Shen-Li ; Chung, Mark C L ; Tseng, Ching-Chung

  • Author_Institution
    Dept. of Mech. & Autom. Eng., I-Shou Univ.
  • fYear
    2006
  • fDate
    26-29 Aug. 2006
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    A novel submodel scheme based on St. Venant´s principle has been developed to evaluate the reliability thermal cycle test (TCT) for CMOS image sensor (CIS). The region of interested in board level CIS package is lead-free paste, which is the peak stressed area to predict fatigue life. A solid finite element model of CIS using ANSYS codes is developed to predict the thermal strain distributions. The predicted thermal-induced displacements were found to be very good agreement with the Moire interferometer experimental in-plane u and v deformations. The developed finite element model is then applied to investigate the reliability of the JEDEC standard JESD22-A104 TCT. In order to save computational time and produce satisfactory results in the coarse region of interest, an independent more finely meshed so-called submodel scheme based on cut-boundary displacement method is generated. The mesh density for different area ratio of submodel/global model was verified and the results were found to be good agreement with previous researches. The modified Coffin-Manson equation is applied to evaluate the predicted fatigue life of SnAgCu pastes. A series of comprehensive parametric studies were conducted in this paper
  • Keywords
    CMOS image sensors; copper alloys; finite element analysis; integrated circuit modelling; integrated circuit reliability; moire fringes; silver alloys; thermal management (packaging); tin alloys; ANSYS codes; CMOS image sensor; Coffin-Manson equation; JEDEC standard; JESD22-A104 TCT; Moire interferometer; SnAgCu; St. Venant principle; board level CIS package; finite element model; in-plane deformations; lead-free paste; reliability thermal cycle test; submodeling scheme; thermal strain distributions; CMOS image sensors; Computational Intelligence Society; Environmentally friendly manufacturing techniques; Fatigue; Finite element methods; Packaging; Predictive models; Semiconductor device modeling; Solid modeling; Testing; CMOS Image Sensor; JEDEC; Moiré Interferometry; Submodel; Thermal Cycle Test;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology, 2006. ICEPT '06. 7th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    1-4244-0619-6
  • Electronic_ISBN
    1-4244-0620-X
  • Type

    conf

  • DOI
    10.1109/ICEPT.2006.359730
  • Filename
    4198851