Title :
Fpga Synthesis With Retiming And Pipelining For Clock Period Minimization Of Sequential Circuits
Author :
Cong, Jason ; Wu, Chang
Author_Institution :
Department of Computer Science University of California, Los Angeles, CA 90095
Keywords :
Circuit synthesis; Clocks; Delay; Field programmable gate arrays; Logic; Minimization; Permission; Pipeline processing; Sequential circuits; Table lookup;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597224
