Title :
Reliability of vertical MOSFETs for gigascale memory applications
Author :
Goebel, B. ; Bertagnolli, E. ; Koch, F.
Author_Institution :
Siemens AG, Munich, Germany
Abstract :
We compare the reliability of vertical MOSFETs with planar ones. For the first time, the impact of the most striking vertical MOS specific features such as different source/drain engineering, channel orientation, and variable gate oxide thickness on reliability is investigated. Even though LDD is missing, it is shown that scaled down vertical transistors have a sufficient reliability for potential use in gigascale memories.
Keywords :
DRAM chips; MOS memory circuits; MOSFET; semiconductor device reliability; semiconductor storage; channel orientation; gigascale memory applications; reliability; scaled down transistors; source/drain engineering; variable gate oxide thickness; vertical MOSFETs; Etching; Lattices; MOSFETs; Manufacturing; Random access memory; Read only memory; Reliability engineering; Shape; Strips; Testing;
Conference_Titel :
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4774-9
DOI :
10.1109/IEDM.1998.746509
