A radiation-hard phase-locked loop

Phase-locked loops (PLLs) are often used as frequency multiplier for generating high frequency clock signals. In space application, however, performance of the normal PLL is degraded due to the radiation effects. In this paper, several aspects of a rad-hard PLL are investigated, including radiation effects, radiation hardening techniques, PLL building blocks and the overall performance. This circuit is developed using the Peregrine 0.50 μm SOS/SOI process. The post-layout simulation result indicates that the circuit can be used to generate 100 M - I80 MHz programmable clock signal under radiation conditions with process, temperature and voltage variations. The maximum peak to peak jitter is less than 100 ps while the maximum lock-in time is less than 20 us under typical conditions.