0.13 /spl mu/m MONOS single transistor memory cell with separated source lines

A 0.13 /spl mu/m MONOS single transistor memory cell is proposed and demonstrated. The three main limiting factors and their solutions in a 0.13 /spl mu/m MONOS single transistor memory cell with separated source lines are clarified. Reduction in the margin of program inhibit voltage due to a short channel effect can be improved by applying a positive bias voltage to unselected wordlines. Leakage current can be reduced by the use of a source bias read technique. Read disturb can be improved with thicker tunnel insulator without increase in program time. An experimental 0.13 /spl mu/m MONOS memory cell is obtained with satisfactory results. A small cell size of about 6F2 (F; feature size) is proposed by the use of winding source lines.