Integration of trench DRAM into a high-performance 0.18 /spl mu/m logic technology with copper BEOL

Author

Crowder, S. ; Hannon, R. ; Ho, H. ; Sinitsky, D. ; Wu, S. ; Winstel, K. ; Khan, B. ; Stiffler, S.R. ; Iyer, S.S.

Author_Institution

Microelectron. Div., IBM Corp., Hopewell Junction, NY, USA

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

1017

Lastpage

1020

Abstract

In this work, we demonstrate the integration of trench DRAM into a 0.18 /spl mu/m copper BEOL technology which is fully compatible with our most advanced logic technology and requires no redesign of preexisting logic circuitry. This technology offers a 0.617 /spl mu/m/sup 2/ DRAM cell on the same chip as a 4.2 /spl mu/m/sup 2/ SRAM cell and dual damascene copper metallization with the highest reported device performance for a 1.5 V bulk silicon technology. We demonstrate a fixable retention time of over 256 ms at 85/spl deg/C for the DRAM cell without any degradation in logic device performance or density.

Keywords

CMOS logic circuits; CMOS memory circuits; DRAM chips; copper; integrated circuit metallisation; 0.18 micron; 1.5 V; 256 ms; 85 C; Cu-Si; DRAM cell; SRAM cell; bulk Si technology; copper BEOL technology; dual damascene Cu metallization; embedded DRAM; high-performance 0.18 /spl mu/m logic technology; trench DRAM integration; Capacitors; Circuit optimization; Conductors; Copper; Implants; Logic arrays; Logic devices; Microprocessors; Random access memory; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746527

Filename

746527