DocumentCode
2576058
Title
Ultra-thin gate oxides and ultra-shallow junctions for high performance, sub-100 nm pMOSFETs
Author
Timp, G. ; Agarwal, Abhishek ; Bourdella, K.K. ; Bower, J. ; Boone, T. ; Ghetti, Andrea ; Green, M. ; Gamo, J. ; Gossmann, H. ; Jacobson, D. ; Kleiman, Rafael ; Kornblit, A. ; Klemens, F. ; Moccio, S. ; O´Malley, M.L. ; Ocola, L. ; Rossm-nalia, J. ; Sapje
Author_Institution
Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
fYear
1998
fDate
6-9 Dec. 1998
Firstpage
1041
Lastpage
1043
Abstract
Reports measurements of the DC characteristics of sub-100nm pMOSFETs that employ low leakage, ultra-thin gate oxides only 1-2nm thick and ultra-shallow junctions to achieve high current drive capability and transconductance. We demonstrate that I/sub Dsct/=0.23mA//spl mu/m can be achieved with a L/sub x/=65nm physical gate length at 15V using a 1.5nm gate oxide with a gate leakage current less than 20nA//spl mu/m/sup 2/ on devices without silicided contacts. But more importantly, we find no evidence of boron penetration through SiO/sub 2/ gate oxides as thin as 1.3nm, grown at 1000C using rapid thermal oxidation (RTO). Furthermore, for the first time, we have directly imaged the ultra-shallow p-n junctions that comprise a sub-100nm pMOSFET with an effective channel length of 20nm to show that the lateral extent of the junction is approximately half that of the vertical junction depth. We surmise that the enhanced vertical diffusion has an adverse effect on subthreshold characteristic of sub-100nm pMOSFETs.
Keywords
MOSFET; insulating thin films; leakage currents; oxidation; semiconductor device measurement; 1 to 2 nm; 1000 degC; 15 V; 15 nm; 65 nm; DC characteristics; SiO/sub 2/; current drive capability; effective channel length; leakage currents; pMOSFETs; physical gate length; rapid thermal oxidation; subthreshold characteristic; ultra-shallow junctions; ultra-thin gate oxides; vertical junction depth; Boron; CMOS technology; Capacitors; Etching; Jacobian matrices; Lithography; MOSFETs; P-n junctions; Silicon; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-4774-9
Type
conf
DOI
10.1109/IEDM.1998.746534
Filename
746534
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