Title :
Post-layout Logic Restructuring For Performance Optimization
Author :
Yi-Min Jiang ; Krstic, A. ; Kwang-Ting Cheng ; Marek-Sadowska, M.
Author_Institution :
University of California, Santa Barbara,CA93106
Keywords :
Benchmark testing; Circuit synthesis; Circuit testing; Convergence; Coupling circuits; Delay estimation; Integrated circuit interconnections; Logic circuits; Logic design; Optimization;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597227
