• DocumentCode
    2576219
  • Title

    Stress Distribution of Stacked Chip Package in Curing Process

  • Author

    Yin, Jinghua ; Wang, Shuqi ; Du, Bing ; Lu, Guangjun ; Liu, Xiaowei

  • Author_Institution
    Harbin Univ. of Sci. & Technol.
  • fYear
    2006
  • fDate
    26-29 Aug. 2006
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    In this paper, packaging process for a typical stacked three-chip packaging structure has been studied in detail by finite element analysis (FEA) method. The simulation shows that thermal stress may result in die crack and delamination before package has been finished. During the each curing process, the stresses of joints of die in the bottom layer are largest and the system reliability is not lowered over three layers die. The package would be destroyed most easily in cure II step. Failure rate of upper die is also high in the cure III, as the epoxy molding compound (EMC) can bring residual stress of phase changing, and combining FEA results, the package structure has been optimized
  • Keywords
    curing; delamination; finite element analysis; integrated circuit packaging; integrated circuit reliability; moulding; thermal stress cracking; curing process; delamination; die crack; epoxy molding compound; finite element analysis; stacked three-chip packaging; stress distribution; system reliability; thermal stress; Chip scale packaging; Curing; Delamination; Electronic packaging thermal management; Electronics packaging; Field emitter arrays; Finite element methods; Temperature; Thermal management; Thermal stresses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology, 2006. ICEPT '06. 7th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    1-4244-0619-6
  • Electronic_ISBN
    1-4244-0620-X
  • Type

    conf

  • DOI
    10.1109/ICEPT.2006.359788
  • Filename
    4198909