A special purpose hybrid SIMD processor for logic event simulation

This paper introduces a hybrid associative memory/SIMD parallel processor, APPLES, which has been specifically designed for logic simulation. It reviews the computational structure which permits parallel execution of logic gate evaluations in memory. This facilitates fine grain execution on a massive scale of the basic tasks inherent in VLSI logic simulation. Furthermore, unlike other SIMD approaches the simulation is not limited to a unit delay model, complex delays such as inertial delays are permissible. The processor has been implemented in Verilog and assessed using ISCAS-85 benchmark. Gate evaluation is executed in constant time, whereas updating fan-out lists expands with circuit size. However, the APPLES architecture enables this latter task to be parallelised subject to various system parameters. The most important constraint is identified as the fan-out memory access time relative to the scan rate of the associative memory