Through Wafer Via Technology for MEMS and 3D Integration

Author

Rimskog, Magnus

Author_Institution

Silex Microsyst., San Francisco, CA

fYear

2007

fDate

3-5 Oct. 2007

Firstpage

286

Lastpage

289

Abstract

The Through Silicon Via (TSV) process developed by Silex offers sub 50 mum pitch for through wafer connections in up to 600 mum thick substrates. The via process enables MEMS designs with significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. With several companies using the process already today and a line-up of potential users, the process is becoming a standard in the MEMS industry. This paper gives a brief introduction to the via formation process and focuses in more detail on the novel solutions made available by this enabling technology.

Keywords

CMOS integrated circuits; integrated circuit interconnections; micromechanical devices; wafer level packaging; 3D integration; 3D interconnect; CMOS integration; MEMS designs; advanced interconnect functions; microfluidic devices; optical MEMS; sensors; through silicon via process; through wafer connections; through wafer via technology; via formation process; wafer level packaging; Integrated optics; Microfluidics; Micromechanical devices; Optical devices; Optical interconnections; Optical sensors; Process design; Silicon; Through-silicon vias; Wafer scale integration; 3d interconnect; CMOS integration; interposer; through silicon via; wafer level packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Manufacturing Technology Symposium, 2007. IEMT '07. 32nd IEEE/CPMT International

Conference_Location

San Jose, CA

ISSN

1089-8190

Print_ISBN

978-1-4244-1335-5

Electronic_ISBN

1089-8190

Type

conf

DOI

10.1109/IEMT.2007.4417078

Filename

4417078