• DocumentCode
    2576962
  • Title

    High-reliability fault-tolerant 16 Mbit memory chip

  • Author

    Stapper, C.H. ; Fifield, J.A. ; Kalter, H.L.

  • Author_Institution
    IBM, Essex Junction, VT, USA
  • fYear
    1991
  • fDate
    29-31 Jan 1991
  • Firstpage
    48
  • Lastpage
    56
  • Abstract
    A combination of redundant circuits and error-correcting-code circuits have been implemented on a 16 Mb memory chip. The combination of these circuits results in a synergistic fault-tolerance scheme, making this chip immune to a high level of manufacturing and reliability defects. In addition to the error-correcting-code circuits, the chip also has redundant cells that can be used to replace defective cells. The combined use of the error-correcting code, and redundancy results in a synergetic fault-tolerance effect, making the chip impervious to thousands of manufacturing defects. This is an increase in fault tolerance of several orders of magnitude
  • Keywords
    circuit reliability; error correction codes; fault tolerant computing; integrated memory circuits; redundancy; 16 Mbit; error-correcting-code circuits; fault tolerant memory chip; high reliability; redundant circuits; synergistic fault-tolerance scheme; Circuit faults; Error correction; Error correction codes; Fault tolerance; Integrated circuit manufacture; Integrated circuit reliability; Manufacturing; Page description languages; Random access memory; Redundancy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability and Maintainability Symposium, 1991. Proceedings., Annual
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-87942-661-6
  • Type

    conf

  • DOI
    10.1109/ARMS.1991.154413
  • Filename
    154413