40Gbps multi-connection TCP/IP offload engine

Author

Ji, Yong ; Hu, Qing-Sheng

Author_Institution

Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China

fYear

2011

fDate

9-11 Nov. 2011

Firstpage

1

Lastpage

5

Abstract

TCP/IP stack is the workhorse protocol of the Internet. The processing of the TCP/IP over Ethernet is traditionally accomplished by software running on the central processor, CPU or microprocessor. As the speed of Ethernet grows from 10Mbits/s to 10Gbits/s, the CPU can´t afford the large amount of TCP/IP protocol processing required. So the TCP/IP protocol processor becomes an efficient and a must method to offload CPU burdens. This paper proposes a TCP/IP Internet protocol processing system architecture, which is to implement transport layer, network layer and data link layer, and support configurable number of connections. The design is implemented on Altera StratixIV FPGA. The performance estimation shows that our system can provide high-speed TCP/IP transmission rate up to 4Gbps as receiver and 40Gbps as sender.

Keywords

Internet; field programmable gate arrays; local area networks; transport protocols; Altera StratixIV FPGA; Ethernet; Internet; TCP/IP protocol; TCP/IP stack; bit rate 40 Gbit/s; multiconnection TCP/IP offload engine; Engines; Field programmable gate arrays; IP networks; Protocols; Receivers; SDRAM; Servers; FPGA; Multi connections; TCP/IP offload engine;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications and Signal Processing (WCSP), 2011 International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4577-1009-4

Electronic_ISBN

978-1-4577-1008-7

Type

conf

DOI

10.1109/WCSP.2011.6096913

Filename

6096913