A Dependable Processor by Using Built-in Self Test to Tolerate Periodical Transient Faults under Highly Electromagnetic Environment

This paper releases a report of the application for the fault tolerant sequential circuit technique against periodical transient faults under highly electromagnetic environment. After implementing the proposed fault tolerant technique on a counter in our previous paper, as an example of how the proposed architecture performs on utility-scale sequential circuits, the result obtained by applying the technique to a processor is illustrated. On the basis of our logic simulation, we confirm that the originally designed 8-bit processor with functional BIST can avoid the periodical multiple transient faults. We further show that sequential circuits with a practical size of a processor can apply the fault tolerant technique with low overhead from the viewpoint of the circuit space.