Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored

In this paper we explore a hierarchical memory architecture that simplifies the WCET prediction of tasks. Instead of using cache memories for speeding up code execution, we propose to use hierarchical memories that are similar to scratchpad memories. These memories are filled by explicit prefetch operations that are executed in synchrony with program execution. The instructions respectively the data that determine both the content and the timing of the operations that perform the memory transfers between the different memory levels are computed at code-generation time. The paper describes the overall system and memory architecture, and design choices for explicitly controlled time-predictable hierarchical memory architectures.