A novel fast DCT coefficient scan architecture

This paper proposes a novel, fast, highly-parallel and configurable architecture for zigzag scan and optional scans in multiple video coding standards, including H.261, MPEG-1,2,4, H.264/AVC, and AVS. Arbitrary scan patterns could be supported by configuring the ROM data, and the proposed architecture can largely reduce the processing cycles. This makes it possible to integrate the scan unit into the transform pipeline stage, thus mode decision could be more efficient. The scanning process is divided into 2 pipeline stages. By introducing parallelism, phase1 generates all temporary-runs of an 8 times 8 block in 16 cycles. In phase2 the number of cycles used to output the final (run, level) pairs is equal to the total number of the nonzero coefficients in a block. The experimental results show the proposed architecture is able to reduce up to 80% of total scanning cycles on average.