Electroless Plating Ni-based Barrier Layers for Silicon Vertical Interconnects

Author

Feng, Guoqiang ; Cai, Jian ; Peng, Xiao ; Wan, Shuidi ; Songliang Jia

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

fYear

2006

fDate

26-29 Aug. 2006

Firstpage

1

Lastpage

3

Abstract

A novel fabrication process for electroless plating NiMoP barrier layer on SiO₂ was presented for 3D packaging with silicon vertical interconnects. The NiMoP film was deposited electrolessly by using a silane coupling agent as an adhesion and catalyzed layer. In addition, a potential NiMoP barrier/seed layer was successfully formed via electroless plating atop SiO₂ after Pd activation. The composition and the electrical resistivity of NiMoP were investigated by scanning electron microscope (SEM) and four-point probe. The barrier layer and seed layer functions of NiMoP were verified by direct Cu electroplating and Auger electron microscope (AES)

Keywords

electrical resistivity; electroplating; integrated circuit interconnections; integrated circuit packaging; scanning electron microscopy; 3D packaging; Auger electron microscope; Ni based barrier layers; NiMoP; SiO₂; barrier layer; electrical resistivity; electroless plating; four point probe; scanning electron microscope; seed layer functions; silicon vertical interconnects; Adhesives; Copper; Fabrication; MOCVD; Packaging; Power system interconnection; Scanning electron microscopy; Silicon; Sputtering; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology, 2006. ICEPT '06. 7th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0619-6

Electronic_ISBN

1-4244-0620-X

Type

conf

DOI

10.1109/ICEPT.2006.359879

Filename

4199000