Chip Parasitic Extraction And Signal Integrity Verification

Author

Dai, Wayne W M

Author_Institution

University of California at Santa Cruz

fYear

1997

fDate

9-13 June 1997

Firstpage

717

Lastpage

719

Keywords

Clocks; Conductors; Delay; Geometry; Logic; Parasitic capacitance; Permission; Solid modeling; Transistors; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the 34th

Conference_Location

Anaheim, CA, USA

ISSN

0738-100X

Print_ISBN

0-7803-4093-0

Type

DOI

10.1109/DAC.1997.597238

Filename

597238

Link To Document