DocumentCode
2578365
Title
A trace driven study of the effectiveness of cache mechanism for network processors
Author
Liu, Zhen ; Che, Hao ; Zheng, Kai ; Chen, Shanzhen ; Liu, Bin
Author_Institution
Dept. of Comput. Sci. & Eng., Tsinghua Univ., Beijing, China
Volume
2
fYear
2005
fDate
23-26 Sept. 2005
Firstpage
978
Lastpage
981
Abstract
Network processor (NP) is a new breed of packet forwarding engine that is designed to meet the simultaneous demands of high speed and great flexibility of today´s network equipments. Cache mechanism has attracted more and more attentions in the field of NP design because of its big success in terms of latency hiding. In this paper, we evaluate the effectiveness of cache mechanism for NP under the new context of packet forwarding using real-life packet traces. Our results suggest that caching can reduce the packet loss rate to an extremely low level under reasonable hit rate and packet buffer size. However, the possibility of incurring large queuing delay makes it unsuitable for applications demanding stringent quality of service (QoS) enforcement. Furthermore, we also show that the combination of cache mechanism with multithreading will be a promising way because of the dramatically decreased both queuing and processing delay, in addition to the even lower packet loss rate.
Keywords
cache storage; computer networks; processor scheduling; quality of service; queueing theory; QoS; cache mechanism; network processors; packet buffer size; packet forwarding; packet loss rate; quality of service; queuing; Access protocols; Added delay; Associative memory; Coprocessors; Engines; Multithreading; Prefetching; Processor scheduling; Quality of service; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communications, Networking and Mobile Computing, 2005. Proceedings. 2005 International Conference on
Print_ISBN
0-7803-9335-X
Type
conf
DOI
10.1109/WCNM.2005.1544215
Filename
1544215
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