A hybrid adiabatic parallel prefix addition scheme for low power

The major constraint in VLSI design is the tradeoff between area, power and speed. Hence, it is very important to obtain an optimal tradeoff among the three parameters. The design approach needed for the ubiquitous adder circuit is of paramount importance. This paper strives in that direction. The generation of carry signal is the most time-consuming process. Literature presents many schemes for faster computation of input carry signals. We have designed CMOS adder using the triple carry operator proposed in the literature. Comparative performance analysis of efficient energy recovery schemes such as 2N2N-2P and PFAL are also presented. The results prove that the proposed adder consumes 46.2% less power at 100 MHz, compared to the CMOS counterpart. The new design methodology also consumes lower power than the adiabatic implementation of other tree adders like Sklansky, Brent-Kung and Kogge-Stone. The simulation is done using TANNER EDA tool. 350nm CMOS technology library file from Austria Micro System have been used in the designs.