Design of avalanche capability of Power MOSFETs by device simulation

Author

Pawel, I. ; Siemieniec, R. ; Rösch, M. ; Hirler, F. ; Geissler, C. ; Pugatschow, A. ; Balk, L.J.

Author_Institution

Infineon Technol. Austria AG, Villach

fYear

2007

fDate

2-5 Sept. 2007

Firstpage

1

Lastpage

10

Abstract

The avalanche behavior of new 150 V trench power MOSFETs was designed with the help of two- dimensional device simulation techniques. The devices employ the compensation principle for low on-state losses. A new edge-termination structure ensures that avalanche breakdown always occurs in the cell region of the device. For the transistor cells, two different destruction regimes were identified: energy-related destruction and current-related destruction. Possible simulation approaches to account for the different effects were proposed. The found dependence on design parameters based on device simulation was qualitatively confirmed by experimental results. Furthermore, strong dependence between on-resistance and avalanche current was shown.

Keywords

avalanche breakdown; power MOSFET; semiconductor device breakdown; 2D device simulation; avalanche breakdown; compensation principle; current-related destruction; edge-termination structure; energy-related destruction; low on-state losses; power MOSFET; voltage 150 V; Amplifiers; Charge carrier processes; Charge carriers; Current measurement; Electron beams; Inductance; Insulation; MOSFETs; Power measurement; Voltage; MOSFET; Measurement; Power semiconductor device; Robustness; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics and Applications, 2007 European Conference on

Conference_Location

Aalborg

Print_ISBN

978-92-75815-10-8

Electronic_ISBN

978-92-75815-10-8

Type

conf

DOI

10.1109/EPE.2007.4417220

Filename

4417220