A Fully Printable, Self-aligned And Planarized Stacked Capacitor DRAM Cell Technology For 1Gbit DRAM And Beyond

Author

Kohyama, Y. ; Ozaki, T. ; Yoshida, S. ; Ishibashi, Y. ; Nitta, H. ; Inoue, S. ; Nakamura, K. ; Aoyama, T. ; Imai, K. ; Hayasaka, N.

Author_Institution

Microelectronics Engineering Laboratory, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235, Japan

fYear

1997

fDate

10-12 June 1997

Firstpage

Lastpage

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-75-1

Type

DOI

10.1109/VLSIT.1997.623673

Filename

623673

Link To Document