Title :
0.25/spl mu/m W-polycide Dual Gate And Buried Metal On Diffusion Layer (BMD) Technology For DRAM-embedded Logic Devices
Author :
Tsukamoto, M. ; Kuroda, H. ; Okamoto, Y.
Author_Institution :
System LSI Division, Semiconductor Company, SONY Corporation 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243, JAPAN
Conference_Titel :
VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on
Print_ISBN :
4-930813-75-1
DOI :
10.1109/VLSIT.1997.623676
