• DocumentCode
    2579343
  • Title

    Notary: Hardware techniques to enhance signatures

  • Author

    Yen, Luke ; Draper, Stark C. ; Hill, Mark D.

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Wisconsin-Madison, Madison, WI
  • fYear
    2008
  • fDate
    8-12 Nov. 2008
  • Firstpage
    234
  • Lastpage
    245
  • Abstract
    Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., bulk, LogTM-SE, and SigTM). Signatures use fixed hardware to represent an unbounded number of addresses, but may lead to false conflicts (detecting a conflict when none exists). Previous work recommends that signatures be implemented with parallel Bloom filters with two or four hash functions (e.g., H3). Two problems exist with current signature designs. First, H3 implementations use many XOR gates. This increases hardware area and power overheads. Second, signature false positives can result from conflicts with signature bits set by private memory addresses that do not require isolation. This paper develops Notary, a coupling of two signature enhancements to ameliorate these problems. First, we use address entropy analysis to develop page-block-XOR (PBX) hashing and show it performs similar to H3 at lower hardware cost. Second, we introduce a privatization interface that explicitly allows the programmer to declare shared and private heap memory allocation. Privatization reduces false conflicts arising from private memory accesses and can lead to a reduction in the signature size used. Results from custom transistor-level layouts of H3 and PBX, along with full-system simulation of a 16-core chip-multiprocessor implementing LogTM-SE, show (a) PBX hashing performs similar to H3 hashing while requiring up to 24% less area and 4.7% less power overhead and (b) privatization can improve execution time by up to 86% (by reducing false conflicts by up to 96%).
  • Keywords
    cryptography; chip-multiprocessors; hardware techniques; hash functions; memory allocation; page-block-XOR gates; parallel Bloom filters; privatization interface; signature enhancement; Concurrent computing; Entropy; Filters; Hardware; Lead; Parallel programming; Privatization; Programming profession; Sun; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on
  • Conference_Location
    Lake Como
  • ISSN
    1072-4451
  • Print_ISBN
    978-1-4244-2836-6
  • Electronic_ISBN
    1072-4451
  • Type

    conf

  • DOI
    10.1109/MICRO.2008.4771794
  • Filename
    4771794