A 0.18/spl mu/m CMOS Process Using Nitrogen Profile-engineered Gate Dielectrics

Author

Grider, D.T. ; Hattangady ; Kraft ; Nicollian, P.E. ; Kuehne, J. ; Brown, G. ; Aur, S. ; Eklund, R.H. ; Pas, M.F. ; Hunter, W.R. ; Douglas, M.

Author_Institution

Semiconductor Process and Device Center and *Materials Science Laboratory Texas Instruments, Inc., P.O. Box 655012, Dallas, TX 75265

fYear

1997

fDate

10-12 June 1997

Firstpage

Lastpage

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-75-1

Type

DOI

10.1109/VLSIT.1997.623688

Filename

623688

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