Title :
Pattern recognition using N-input neuron circuits based on floating gate MOS transistors
Author :
Keles, Fatih ; Yildirim, T.
Author_Institution :
Comput. Eng. Dept., Yildiz Tech. Univ., Istanbul, Turkey
Abstract :
In this paper, a neural network hardware implementation of pattern recognition using n-input neuron circuits is presented. Floating-gate MOS (FGMOS) based neuron model using four-quadrant analog multiplier with rail-to-rail linear input and FGMOS based differential comparator has been designed and simulated in HSPICE environment. Using the proposed low voltage neuron circuits a neural network was realized. Iris plant data set, which is one of the most well-known pattern recognition databases, was applied to test accuracy of the network.
Keywords :
MOSFET; SPICE; analogue multipliers; network synthesis; neural nets; pattern recognition; FGMOS based differential comparator; FGMOS based neuron model; HSPICE environment; Iris plant data set; N-input neuron circuits; floating gate MOS transistors; four-quadrant analog multiplier; neural network; neural network hardware; pattern recognition; Circuit simulation; Databases; Iris; Low voltage; MOSFETs; Neural network hardware; Neural networks; Neurons; Pattern recognition; Rail to rail inputs; FGMOS transistors; Neuron circuits; classification; hardware implementations; neural network; pattern recognition;
Conference_Titel :
EUROCON 2009, EUROCON '09. IEEE
Conference_Location :
St.-Petersburg
Print_ISBN :
978-1-4244-3860-0
Electronic_ISBN :
978-1-4244-3861-7
DOI :
10.1109/EURCON.2009.5167634
