Analysis and design of a 3–5 GHZ ultra-wideband CMOS low-noise amplifier

This paper presents the design and analysis of a 3-5 GHz ultra-wideband (UWB) low-noise amplifier (LNA) in a 0.18 mum CMOS process. The proposed LNA consists of two stacked common-source stages which enable sufficient gain and wide operating bandwidth. Simulation results show a power gain of 14 dB with a variation less than 0.5 dB over 3-5 GHz, input and output return loss lower than -9 dB and -8.5 dB, respectively, and noise figure lower than 2.4 dB in the band of interest. The input-referred 1-dB compression point (P_1dB), IIP3, and power consumption of the LNA are about -18 dBm, -4 dBm and 12 mW, respectively.