Title :
A PLL frequency multiplier for LVDS transmitter
Author :
Tao, Zhang ; Xuecheng, Zou ; Xubang, Shen
Author_Institution :
Inst. of Pattern Recognition & Artificial Intelligence, Hubei, China
Abstract :
A. 3.5 times PLL clock frequency multiplier for LVDS driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth, and a VCO is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25μm mixed-signal CMOS process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time.
Keywords :
CMOS integrated circuits; data communication equipment; driver circuits; frequency allocation; frequency multipliers; mixed analogue-digital integrated circuits; phase locked loops; transmitters; voltage-controlled oscillators; 0.25 mum; LVDS transmitter; PLL frequency multiplier; frequency ranges reuse technology; mixed-signal CMOS process; Bandwidth; CMOS technology; Charge pumps; Clocks; Driver circuits; Frequency; Phase locked loops; Switches; Transmitters; Voltage-controlled oscillators;
Conference_Titel :
Wireless Communications, Networking and Mobile Computing, 2005. Proceedings. 2005 International Conference on
Print_ISBN :
0-7803-9335-X
DOI :
10.1109/WCNM.2005.1544319
