DocumentCode :
2580291
Title :
A unified architecture for efficient data and Non-Data Aided frequency estimation for FPGA implementation and application to satellite communications
Author :
Ramakrishnan, Balasubramanian ; Long, Jeffrey P.
Author_Institution :
MITRE Corp., Bedford, MA, USA
fYear :
2010
fDate :
21-23 April 2010
Firstpage :
1
Lastpage :
9
Abstract :
Modern codes such as Turbo and LDPC codes operate at low signal-to-noise ratios, which makes carrier synchronization a challenging problem. Hence in many waveforms, some known symbols are inserted periodically into the data stream to achieve Data-Aided (DA) synchronization. However, these known symbols decrease the throughput of the transmissions. The data symbols which are unknown can also be used for synchronization, in which case it is known as Non-Data Aided (NDA) synchronization. In this paper, we present an efficient structure which is almost the same for both the DA and NDA methods,especially suitable for implementation on Field Programmable Gate Arrays (FPGA). We discuss the implementation complexity and trade-offs involved in the FPGA implementation of this structure. We illustrate its utility by applying it a satellite communications waveform, popularly known as DVB-S2.
Keywords :
field programmable gate arrays; parity check codes; satellite communication; turbo codes; DVB-S2; FPGA implementation; LDPC codes; data aided frequency estimation; field programmable gate arrays; nondata aided frequency estimation; satellite communications; turbo codes; Digital video broadcasting; Field programmable gate arrays; Frequency estimation; Frequency synchronization; Parity check codes; Phase estimation; Phase locked loops; Satellite communication; Signal to noise ratio; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wireless Telecommunications Symposium (WTS), 2010
Conference_Location :
Tampa, FL
ISSN :
1934-5070
Print_ISBN :
978-1-4244-6558-3
Type :
conf
DOI :
10.1109/WTS.2010.5479672
Filename :
5479672
Link To Document :
بازگشت