Title :
Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed
Author :
Naderi, A. ; Mojarrad, H. ; Ghasemzadeh, H. ; Khoei, A. ; Hadidi, Kh
Author_Institution :
Electr. Eng. Dept., Urmia Univ., Urmia, Iran
Abstract :
In this paper a new CMOS current-mode four-quadrant analog multiplier circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 mum standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.15%, a THD of 0.76% in 1 MHz, a -3 dB bandwidth of 44.9 MHz and a maximum power consumption of 0.24 mW.
Keywords :
CMOS analogue integrated circuits; analogue multipliers; CMOS current-mode; HSPICE simulator; bandwidth 44.9 MHz; current squarer circuit; dual translinear loop; four-quadrant CMOS analog multiplier; power 0.24 mW; size 0.35 mum; voltage 3.3 V; Bandwidth; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Energy consumption; Integrated circuit technology; Linearity; MOSFETs; Power dissipation; Voltage; CMOS analog multiplier; current mode; four quadrant; squarer circuit; translinear loop;
Conference_Titel :
EUROCON 2009, EUROCON '09. IEEE
Conference_Location :
St.-Petersburg
Print_ISBN :
978-1-4244-3860-0
Electronic_ISBN :
978-1-4244-3861-7
DOI :
10.1109/EURCON.2009.5167644
