Title :
Interconnect Scaling Scenario Using A Chip Level Interconnect Model
Author :
Yamashita, K. ; Odanaka, S.
Author_Institution :
Semiconductor Research Center, Matsushita Electric Industrial Co.,Ltd. 3-1-1, Yagumo-nakamachi, Moriguchi, Osaka 570, Japan
Conference_Titel :
VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on
Print_ISBN :
4-930813-75-1
DOI :
10.1109/VLSIT.1997.623691
