A Simple Sub-0.3/spl mu/m CMOS Technology With Five-level Interconnect Using Al-plug And HSQ Of Low-k For High Performance Processor

Author

Yoshiyama, K. ; Okada, K. ; Igarashi, M. ; Yamada, K. ; Shimizu, S. ; Takata, Y. ; Osaki, A. ; Higashitani, K. ; Asai, S.

Author_Institution

ULSI Laboratory, Mitsubishi Electric Corporation 4-1 Mizuhara, Itami, Hyogo 664, JAPAN

fYear

1997

fDate

10-12 June 1997

Firstpage

Lastpage

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-75-1

Type

DOI

10.1109/VLSIT.1997.623692

Filename

623692

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