Fully integrated 50 Gbit/s half-rate linear phase detector in SiGe BiCMOS

This paper presents a fully integrated half-rate linear phase detector for clock and data recovery (CDR) in serial communication systems which is capable of operating up to 50 Gbit/s. Because of its half-rate architecture, the phase detector features inherent 1:2 demultiplexing. Also, a charge pump and a simple loop filter is integrated on-chip, which allows characterizing the performance of the phase detector. At a core supply voltage of 3.3 V and an input bias voltage of 3.6 V, the total power consumption of the integrated circuit amounts to 1.22 W. Using a 0.25 μm SiGe HBT BiCMOS technology, the chip core area occupies 1.1×0.8mm².