DocumentCode :
2581118
Title :
An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection
Author :
Hsiao, Pei-Yung ; Li, Le-Tien ; Chen, Chia-Hsiung ; Chen, Szi-Wen ; Chen, Sao-Jie
Author_Institution :
Dept. of Electron. Eng., Chang Gung Univ., Tao Yuan, Taiwan
fYear :
2005
fDate :
15-16 Aug. 2005
Abstract :
In this paper we present an FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. The system contains two edge detection algorithms which are suitable for hardware realization and insensitive to noise. The two adopted algorithms are able to produce different outputs suitable for different applications. A controller which integrates parameter setting, continuous edge detection task processing and output selection is proposed. The proposed modified LGT algorithm not only preserves the original edge detection performance, but also greatly reduces the use of hardware resource. We adopt FPGA design flow as our early-stage verification platform, and result in a maximum working frequency of 54 MHz, which is able to process 205 512×512 grayscale images, and is 90 times faster than the software execution.
Keywords :
edge detection; field programmable gate arrays; image processing equipment; real-time systems; 54 MHz; FPGA architecture design; LGT algorithm; continuous edge detection; grayscale images; output selection; parameter setting; parameter-adaptive real-time image processing system; Algorithm design and analysis; Control systems; Detectors; Field programmable gate arrays; Hardware; Image edge detection; Image processing; Intelligent systems; Intelligent vehicles; Real time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Emerging Information Technology Conference, 2005.
Print_ISBN :
0-7803-9328-7
Type :
conf
DOI :
10.1109/EITC.2005.1544366
Filename :
1544366
Link To Document :
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