DocumentCode
2581139
Title
SoC infrastructure IP´s
Author
Kao, Chung-Fu ; Huang, Shyh-Ming ; Chen, Chun-Chang ; Huang, Ing-Jer
Author_Institution
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear
2005
fDate
15-16 Aug. 2005
Abstract
This paper introduce three infrastructure IP modules in an SoC design. These IP modules are retargetable embedded in-circuit emulation (ICE) module, real-time hardware trace compressor, and on-chip bus platform. The retargetable ICE module is parameterized and can integrate with different microprocessors. The embedded real-time tracer compresses the memory addresses referenced and transfers trace data to external off-chip storage in real-time. The on-chip bus platform can speedup the IP modules integration and reduce the system verification complexity.
Keywords
industrial property; logic design; logic testing; microprocessor chips; real-time systems; system buses; system-on-chip; IP module integration; SoC design; SoC infrastructure IP; memory address; microprocessors; on-chip bus platform; real-time hardware trace compressor; retargetable embedded in-circuit emulation module; system verification complexity; Clocks; Computer architecture; Emulation; Hardware; Ice; Microprocessors; Software debugging; System buses; System-on-a-chip; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging Information Technology Conference, 2005.
Print_ISBN
0-7803-9328-7
Type
conf
DOI
10.1109/EITC.2005.1544367
Filename
1544367
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