Title :
Reconfigurable shape-adaptive template matching architectures
Author :
Gause, Jörn ; Cheung, Peter Y K ; Luk, Wayne
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
Abstract :
This paper presents reconfigurable computing strategies for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video frames. A generic systolic array architecture is proposed as the basis for comparing three designs: a static design where the configuration does not change after compilation, a partially-dynamic design where a static circuit can be reconfigured to use different on-chip data, and a dynamic design which completely, adapts to a particular computation. While the logic resources required to implement the static and partially-dynamic designs are constant and depend only on the size of the search frame, the dynamic design is adapted to the size and shape of the template object, and hence requires much less area. The execution time of the matching process greatly depends on the number of frames the same object is matched at. For a small number of frames, the dynamic and partially-dynamic designs suffer from high reconfiguration overheads. This overhead is significantly reduced if the matching process is repeated on a large number of consecutive frames. We find that the dynamic SA-TM design in a 50 MHz Virtex 1000E device, including reconfiguration time, can perform almost 7,000 times faster than a 1.4 GHz Pentium 4 PC when processing a 100×100 template on 300 consecutive video frames in HDTV format.
Keywords :
field programmable gate arrays; image matching; reconfigurable architectures; systolic arrays; Virtex 1000E device; compilation; generic systolic array architecture; logic resources; matching process; partially-dynamic design; reconfigurable computing strategies; reconfigurable shape-adaptive template matching architectures; shape-adaptive template matching method; video frames; Computer architecture; Educational institutions; Electrical capacitance tomography; Hardware; Head; Hip; Logic; Shape; Systolic arrays; Tellurium;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2002. Proceedings. 10th Annual IEEE Symposium on
Print_ISBN :
0-7695-1801-X
DOI :
10.1109/FPGA.2002.1106665