Title :
The ideal SoC memory: 1T-SRAMTM
Author :
Leung, Wingyu ; Hsu, Fu-Chieh ; Jones, Mark-Eric
Author_Institution :
MoSys Inc., Sunnyvale, CA, USA
Abstract :
The advances of process technology makes system-on-a-chip a reality and present major challenge to IC design. Integration of memory in SoC is further complicated by the incompatibility of memory process technology to the logic process. The simplicity of 1T-SRAM cell facilitates its easy porting to most processes. This helps alleviate the problem of process incompatibility. The simplicity of the cell structure also makes it extremely scalable and cost effective. The challenges of using this cell to satisfy the requirement of embedded SRAM are high-frequency operation, short latency, transparent refresh and soft-error rate. The use of multi-bank architecture and the leverage of multi-layer metal interconnect available in logic processes, allow these challenges to be met readily
Keywords :
VLSI; application specific integrated circuits; integrated memory circuits; microprocessor chips; random-access storage; 1T-SRAM cell; ASIC; IC design; SoC memory; cost effective cell; embedded SRAM; high-frequency operation; logic process; memory process technology; multi-bank architecture; multi-layer metal interconnect; process incompatibility; scalable memory cell; short latency; soft-error rate; system-on-a-chip memory; transparent refresh; Application specific integrated circuits; Costs; Delay; Logic; MOS capacitors; Process design; Random access memory; Silicon; Standardization; System-on-a-chip;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880671
