Silicon-level Solutions to Counteract Passive and Active Attacks

Author

Guilley, Sylvain ; Sauvage, Laurent ; Danger, Jean-Luc ; Selmane, Nidhal ; Pacalet, Renaud

Author_Institution

TELECOM ParisTech, Dept. COMELEC, Inst. TELECOM, Paris

fYear

2008

fDate

10-10 Aug. 2008

Firstpage

3

Lastpage

17

Abstract

This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics.The purpose of these prototype circuits is to experience with the published ``implementation-level´´ attacks(SPA, DPA, EMA, templates, DFA). We report our conclusions about the practicability of these attacks:which ones are the most simple to mount, and which ones require more skill, time, equipments, etc.The potential of FPGAs as security evaluation commodities at design time is also detailed.Then, we discuss about ``dual counter-measures´´, that are meant to resist both passive and active attacks.This study started four years ago with TIMA (Grenoble), in the framework of the project MARS. We highlight some research directions towards dependable and cost-effective dual counter-measures.

Keywords

CMOS integrated circuits; application specific integrated circuits; cryptography; field programmable gate arrays; CMOS technology; FPGA; Grenoble; STMicroelectronics; SecMat; TIMA; active attacks; cryptographic ASIC; dual counter-measures; passive attacks; project MARS; security evaluation; silicon-level solutions; size 130 nm; CMOS technology; Cryptography; Doped fiber amplifiers; Field programmable gate arrays; Hardware; Information retrieval; Page description languages; Prototypes; Resists; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault Diagnosis and Tolerance in Cryptography, 2008. FDTC '08. 5th Workshop on

Conference_Location

Washington, DC

Print_ISBN

978-0-7695-3314-8

Type

conf

DOI

10.1109/FDTC.2008.18

Filename

4599552