A DFE equalizer ASIC chip using the MMA algorithm

Author

Shin, DaeKyo ; Park, Ki Hyuk ; Sunwoo, Myung H.

Author_Institution

Ajou Univ., Suwon, South Korea

fYear

2000

fDate

2000

Firstpage

70

Lastpage

74

Abstract

This paper proposes an equalizer using MMA (Multi-Modulus Algorithm) and LMS (Least Mean Square) algorithms and uses a DFE (Decision Feedback Equalizer) structure. The existing MMA equalizer uses two transversal filters but the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. The fabricated equalizer ASIC chip using MMA and LMS algorithms operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The chip uses the 0.35 μm technology and has about 160,000 gates

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; decision feedback equalisers; digital filters; digital signal processing chips; error statistics; least mean squares methods; parallel architectures; telecommunication computing; 0.35 micron; 64 Mbit/s; 8 MHz; BER; DFE ASIC chip; DFE filter banks; LMS algorithm; MM algorithm; bit error rate; channel adaptive performance; decision feedback equalizer; least mean square algorithm; multi-modulus algorithm; Adaptive algorithm; Application specific integrated circuits; Bit error rate; Blind equalizers; Constellation diagram; DSL; Decision feedback equalizers; Least squares approximation; Probability distribution; Steady-state;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6598-4

Type

conf

DOI

10.1109/ASIC.2000.880678

Filename

880678