Improved VLSI designs for multiplication and inversion in GF(2M) over normal bases

Finite field arithmetic circuits are a core part for implementing some cryptographic systems and Reed-Solomon codes. In this paper, improved VLSI designs for computing multiplication and inverse in GF(2 ^m) over normal bases are presented. The improvements over the previous publications for the Massey-Omura multiplier include both circuit and architecture (or logic) levels. At circuit level, the improved design reduces the area and power consumption, and is faster than the previous design. At architecture level, the new design reduces logic complexity and is more regular, which, in turn, allows static CMOS design and reduces power dissipation. The latency of the inversion method is reduced with parallelism exploration at no cost in hardware. Therefore, the work presented in this paper can provide better VLSI designs in terms of performance and power consumption