DocumentCode
2581583
Title
Low level watermarking of VLSI designs for intellectual property protection
Author
Irby, David L. ; Newbould, Rexford D. ; Carothers, Jo Dale ; Rodriguez, Jeflrey J. ; Holman, W. Timothy
Author_Institution
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear
2000
fDate
2000
Firstpage
136
Lastpage
140
Abstract
We propose a method for watermarking, called “fingermarking”, for integrated circuit design at the physical design level. The watermark is embedded in the transistor layout, making our method applicable to digital, analog, and mixed-signal SOC designs. We show that a robust watermark can be applied to many designs, and can be implemented with little or no cost in circuit area or performance
Keywords
VLSI; application specific integrated circuits; copy protection; industrial property; integrated circuit design; mixed analogue-digital integrated circuits; VLSI designs; circuit area; fingermarking; integrated circuit design; intellectual property protection; low level watermarking; mixed-signal SOC designs; physical design level; transistor layout; Circuits; Costs; Field programmable gate arrays; Intellectual property; Logic design; Protection; Reverse engineering; Robustness; Very large scale integration; Watermarking;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location
Arlington, VA
Print_ISBN
0-7803-6598-4
Type
conf
DOI
10.1109/ASIC.2000.880690
Filename
880690
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