Title :
Design and test of decision feedback equalizers for 80 Gbit/s bit rate and beyond
Author :
Awny, A. ; Thiede, A. ; Scheytt, J. Christoph
Author_Institution :
Dept. Of High-Freq. Electron., Univ. of Paderborn, Paderborn, Germany
Abstract :
Modification of the 1-tap parallel look-ahead decision feedback equalizer (DFE) architecture is developed using Boolean algebra to enable its operation at 80 Gbps and beyond. Measurement techniques which can be generally applied to the testing of this as well as to other DFE architectures are devised. The equalizer´s wide band clock distribution network enables its operation from 25 to 80 Gbps. The equalizer is designed in a 0.13μm SiGe:C BiCMOS technology, dissipates 4W and occupies 2mm2.
Keywords :
BiCMOS analogue integrated circuits; Boolean algebra; Ge-Si alloys; carbon; decision feedback equalisers; 1-tap parallel look-ahead decision feedback equalizer architecture; BiCMOS technology; Boolean algebra; DFE architecture; SiGe:C; bit rate 20 Gbit/s to 80 Gbit/s; measurement techniques; power 4 W; size 0.13 mum; wide band distribution clock network; Bit error rate; Bit rate; Clocks; Decision feedback equalizers; Delay; Optical receivers; Mixed analog digital integrated circuits; adaptive equalizers; amplitude shift keying; decision feedback equalizers; intersymbol interference; optical receivers; silicon germanium;
Conference_Titel :
Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-61284-754-2
Electronic_ISBN :
0149-645X
DOI :
10.1109/MWSYM.2011.5972591
