Coware pipelining for exploiting intellectual properties and software codes in processor-based designs

Growing requirements on the correct design of high-performance systems in a short time force us to use IP´s in many designs. In this paper, we propose a pipelining technique, called coware pipelining, to efficiently use IP´s in ASIP designs such that the application program meets the performance constraints with minimum cost. The coware pipelining is an extended version of the software pipelining to take into account IP´s and software codes simultaneously. The proposed approach can increase parallelism among tasks significantly over the original one and can lead to better use of IP´s, while the previous state-of-the-art approaches can exploit only the original parallelism represented in the application program. The experimental results on real applications show the efficiency of the proposed method in exploiting IP´s